Solvline Eddy DK Manuel d'utilisateur Page 14

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Eddy DK Programmer Guide
14
J1 Pin Description
Pin No
Name
DK v2.1
Pin No
Expansion
Header Pin No
Description
1
PA5
J10_1
J4_2
Peripheral A : CTS2
UART #2 Clear to Send Signal
Peripheral B : MCBD1
Disabled.
Data Flash connected with SPI0 is used for Eddy-CPU v2.1/v2.5. For
this reason SPI0 and MCDB0, MCDB3, and MCCDB signals,
multiplexing, cannot be used, thus Multimedia Card Slot B is disabled.
2
PA4
J10_2
J4_1
Peripheral A : RTS2
UART #2 Request to Send Signal
Peripheral B : MCDB2
Disabled.
3
PC5
J10_3
J4_12
Peripheral A : A24
External Address Bus
Peripheral B : SPI1_NPCS1
SPI1(Serial Peripheral Interface) Peripheral Chip Select 1
4
PC19
J10_4
J4_24
Peripheral A : A24
Multimedia Card Slot B Data
Peripheral B : SPI1_NPCS2
SPI1(Serial Peripheral Interface) Peripheral Chip Select 2
5
PC21
J10_5
J4_26
Peripheral A : D21
External Data bus
Peripheral B : EF100
Ethernet(WAN) Force 100Mbit/sec.
6
PC23
J10_6
J4_28
Peripheral A : D23
External Data Bus
7
HDMA
J10_7
J1_27
USB Host Port A Data -
8
NC
J10_8
--
Not Connect
9
HDPA
J10_9
J1_29
USB Host Port A Data +
10
DDM
J10_10
-
USB Device Port Data -
11
PC26
J10_11
-
D26
External Data Bus
12
DDP
J10_12
-
USB Device Port Data +
13
PC4
(RDY#)
J10_13
J4_11
Eddy-DK v2,1 : RDY#(OUT)
Ready signal. Output signal for CPU operation status
Peripheral A : A23
External Address Bus
Peripheral B : SPI1_NPCS2
SPI1(Serial Peripheral Interface) Peripheral Chip Select 2
14
PC16
(nRESET)
J10_14
J4_21
Eddy-DK v2,1 : nRESET#(IN)
Polling Input signal continually from External Reset key, implement as
below with checking the constant time of "Low."
Less than 5 seconds: General reset function.
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